Indian Journal of Public Health Research & Development
Year : 2018, Volume : 9, Issue : 10
First page : ( 1037) Last page : ( 1040)
Print ISSN : 0976-0245. Online ISSN : 0976-5506.
Article DOI : 10.5958/0976-5506.2018.01269.X

Competitive and fidelity fixed point updatable FFT processors of vlsi design

Reddy K. Venkatramana¹, Prathap P.¹, Lebaka Sivaprasad¹

¹Asst. Prof., Dept. of ECE, Sri Venkateswara College of Engineering and Technology, Chittoor, Andhra Pradesh, India

Online published on 1 November, 2018.

Abstract

In communication system Fast Fourier Transform (FFT) performs a vital operation and competitive and fidelity fixed point updatable FFT processors of VLSI design has been proposed. Competitive and fidelity fixed point operation done by the use of CSLA (Carry Select Adder). The number of addition and multiplication operation has been performed by FFT algorithm. Mixed radix-3, 4 FFT has been proposed in this method and CSLA shrink the hardware consumption of the scheme and CSLA incorporated into pipelined SDF-SDC. In proposed method, carry select adder has been modified by reduced full adder circuit which provides reduction in slices, delay and power utilization. Number of logic gates utilization has been reduced in the full adder circuit. ModelSim 6.3C has been used to approximate the Simulation of projected competitive and fidelity fixed point updatable Radix-3, 4 SDF-SDC FFT using Carry Select Adder of VLSI design designs and Xilinx ISE10.1 design tool used to validate the performances.

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Keywords

Single path Delay Commutator (SDC), Carry Select Adder (CSLA). Fast Fourier Transform (FFT), Single path Delay Feedback (SDF).

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