Implementation of Low Power LFSR's Design through the use of GDI Method Mala P Soundarya1, Srigiri Ch2, Kumar R Jayaram3, Vaddi Srivani4 1Professor Department of ECE, Godavari Institute of Engineering & Technology, Rajahmundry, A.P, India 2Associate, Professor, Department of ECE, Godavari Institute of Engineering & Technology, Rajahmundry, A.P, India 3Asst. Professor, Department of ECE, Godavari Institute of Engineering & Technology, Rajahmundry, A.P, India 4Asst. Professor, Department of ECE, Godavari Institute of Engineering & Technology, Rajahmundry, A.P, India Online published on 2 February, 2019. Abstract The Linear Feedback Shift Register is utilized in testing for ASIC chips by producing pseudo random patterns. This compacts with low power LFSR's design through the use of GDI method. The GDI method is the low power technique utilized to executing the different advanced circuits. This method utilizes 2 transistors to confgure quick and low power circuitswith enhancement in features of power. The conventional and GDI technique is used to execute the LFSR in Cadence Virtuoso at 90nmtechnology. In previous work 4-bit LFSR is designed in cadence tool in 90nm technology and we are proposing the same work in 8-bit LFSR in 45nm cadence tool. The power and delay values are calculated and compared with traditional CMOS logic. Comparative analysis shows up to 45.4% in power in Gate Diffusion Input technique. The area of the circuit is reduced in this technique when compared to CMOS. The analysis shows the 20% reduction in area. In chip manufacturing method, diminishment in size of chip retains great concern for power dissipation. The testing of low power has become a signifcant problem like power dissipation through testing mode will be high as compare with typical mode. Hence the GDI technique is most effcient than CMOS. Top Keywords Logic Gates, Transistors, CMOS technology, VLSI, Built in self test. Top |