Advance TMR and Clock Gating Technique to Design Fault Tolerant ALU Babu Ch R1, Kumar K Ravi1, Abdul Shaik2, Kishore Appala Ratna2 1Associate Professor, Department of ECE, Godavari Institute of Engineering & Technology, Rajahmundry, A.P, India 2Assistant Professor, Department of ECE, Godavari Institute of Engineering & Technology, Rajahmundry, A.P, India Online published on 2 February, 2019. Abstract This investigate paper proposes those latest progresses in the semiconductor industry have headed in the advancement for additional unpredictable segments and systems’ architectures Eventually high number of transistors permitting creation procedures with put An higher number from claiming transistors for every zone of the silicon pass on. Accordingly the manufacturing transform would be less and less reliable. Thusly we need will manufacture frameworks that will recognize the presence from securing faults and fuse strategies will endure these faults same time even now delivering a adequate level for administration. In this paper we available the plan and Investigation from claiming issue tolerant 32-bit math Furthermore legitimate unit circlet outlined utilizing those traditional TMR (Triple modular Redundancy) procedure. Also we confguration ALU to attain achieved energy utilization and profoundly dependable utilizing clock Gating. Top Keywords A.L.U, BCH Code, Fault Tolerance, VHDL, Cadence. Top |