A Novel Architecture For An Efficient Data Encryption System Bhaskar R.*, Ramakrishna A.**, Venkateshwarlu K., Haribabu M. Department of Electrical & Electronics Engineering, Vardhaman College of Engineering, Shamshabad, Hyderabad, India *bhaskar767@gmail.com
**adiraju2662@gmail.com
Online published on 4 November, 2017. Abstract The standard techniques for providing privacy and security in data networks include encryption/decryption algorithms such as Advanced Encryption System (AES) (private-key) and RSA (public-key). RSA is one of the safest standard algorithms, based on public-key, for providing security in networks. Even though the RSA Algorithm is an old and simple encryption technique, there is a scope to improve its performance. One of the most time consuming processes in RSA encryption/decryption algorithm is the computation of ab mod n where “a” is the text, (b, n) is the key. Generally the prime number used for RSA Encryption system will around 100 to 150 decimal digits. The computations involved are tedious and time consuming. Also the hardware is quite complex. To increase the computation speed, the multiplication principle of Vedic mathematics is used and also an improvement is made in the conventional restoring algorithm which does the modulus operation. “Urdhva-tiryakbhyam” is the sutra (principle) which used to compute the multiplication. It literally means vertical and crosswise manipulation. The significance of this technique is that it computes the partial products in one step and avoids the shifting operation which saves both time and hardware. Also an improvement is made in the restoring algorithm by avoiding unnecessary restorations when they are not required. The Verilog HDL code is simulated and synthesized in ModelSim 6.5 and Xilinx ISE 12.1 version tools respectively. Top Keywords AES, RSA, Xilinx, ASSPs. Top |