Analysis of Power and Delay in CMOS Universal Gates using Single Virtual Rail Clamping Technique Kesavan S. P.*, Rajeswari R.** *Assistant Professor, Nandha College of Technology, Erode, Tamilnadu, India **Assistant Professor, Government College of Technology, Coimbatore, Tamilnadu, India Online published on 14 October, 2016. Abstract Power consumption is a major issue in low-voltage, low-power, and high-performance Applications and it is notified as one of the significant challenges in International Technology Roadmap for Semiconductor 2008. In this brief, we use single virtual rail clamping technique, which consist of two different techniques (ie), Header virtual rail clamping (HVRC) and footer virtual rail clamping technique (FVRC) to reduce power consumption of universal gates. The circuits are designed and executed in standard EDA tool with 180nm technology. Results show that the header virtual rail clamping (HVRC) and footer virtual rail clamping (FVRC) NAND logic 2×reduce the power consumption compared to conventional logic, 6× DML type A logic and 16× DML type B logic. The footer virtual rail clamping of NAND logic 18× reduce the power consumption compared to DML type B logic. Performance of HVRC and FVRC NAND logic is 10% and 5% less respectively compared to other logics. The HVRC of NAND logic gives 7× speed improvement as compared to conventional NAND logic 6 × speed improvement as compared to DML logics and FVRC NAND logic has very less delay compared to other logics. The average power consumption of NOR logic in HVRC and FVRC is 1.7× and 1.3× high respectively compared to conventional logic but compared to the DML type A the HVRC NOR logic 5× reduce the power consumption and 1.7× compared to the DML type B, In FVRC NOR logic 6.5× reduce the power consumption compared to the DML type A, 2× compared to the DML type B. The Performance of HVRC and FVRC of NOR logic are 10% less compared to other logic. HVRC NAND and NOR logic has achieved higher speed compared to other logic with which has less power consumption compared to the DML logic. Top Keywords Low-power design, power estimation, performance, low voltage, Delay. Top |