Asian Journal of Research in Social Sciences and Humanities
Year : 2016, Volume : 6, Issue : 10
First page : ( 260) Last page : ( 275)
Online ISSN : 2249-7315.
Article DOI : 10.5958/2249-7315.2016.01012.1

Design and Analysis of Area & Energy Efficient Approximate Multiplier

Revathy M.*, Sudha S.**

*Assistant Professor, Department of ECE, PSNACET, Dindigul

**PG Scholar, Department of ECE, PSNACET, Dindigul

Online published on 14 October, 2016.

Abstract

Approximate (or) inexact computation plays a vital role in the energy efficient digital systems design, particularly interesting paradigm in computer arithmetic designs. The approximate multiplier for multiplication has been designed using two different new approximate 4–2 compressor designs and dadda multiplier. Also NAND based has been designed for analysis. Though multipliers have more number of features, they are considered as a slowest and area consuming element. Fast multipliers are employed in many high performance systems. For the choice of efficient multiplier in area and energy, new approach has been introduced, in which Segmentation of the original operands with significant bits has been done, and performing the multiplication only for those segments is the main principle. In this method multiplier consumes lesser area along with computational error which improves the computational accuracy. The simulation results are implemented by Xilinx ISE design suite 13.2.

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Keywords

Very Large Scale Integration (VLSI), DSP, Approximate (or) inexact computation, truncation, Dadda multiplier.

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