SRAM Cell Memory Design for Power Reduction using Low Power Techniques Rukkumani V*, Devarajan R** *Sri Ramakrishna Engineering College, Coimbatore, India **Government College of Technology, Coimbatore, India Online published on 9 November, 2016. Abstract SRAM memory cell consists of many input signals like precharge, write enable, sense amplifier enable, read enable and row and column encoders. To develop a novel SRAM design, different transistor circuits are available. Normally SRAM cell uses conventional 4 transistor circuit in low power applications. In this thesis, instead of conventional circuit, 8 transistor (8T) and ten transistor(10T) designs are tried to improve the power efficiency under various temperature conditions. Initially 8T and 10T SRAM circuits are designed with write driver logic and the power is calculated for both static and dynamic conditions. Then, charge recycling logic is tried along with precharge logic with various temperature ranges. From the design, total power, static power, dynamic power, Transient time, transient delay and static current in 8T SRAM and 10T SRAM cell are calculated and compared. The 8T SRAM has the least transistor count and least area efficient, but speed of operation is somewhat reduced. Further, increase in the transistor count in 10T SRAM cell, however, makes area and delay large in room temperature. When temperature increases from a particular value, the 10T SRAM cell performs better than the 8T SRAM cell. This justifies the use of 10T SRAM cell for low power applications with varying temperature conditions. The proposed SRAM memory design can be implemented in any digital circuit. Top Keywords SRAM cell, 8T/10T, EDA tool, CMOS technology, Write driver circuit, Charge Recycling logic, Precharge Scaling technique. Top |