Modeling of Redundancy Analyzer in Built In Self Repair for RAMs Sujana Ragi*, Rani M. Asha** JNTUH College of Engineering, Hyderabad *sujana1651989@gmail.com
**ashajntu1@yahoo.com
Online published on 27 June, 2017. Abstract Embedded memories are among the most widely used cores in current SoC implementation. Memory cores usually occupy a significant portion of the chip area, and dominate the manufacturing yield of the chip. Efficient yield-enhancement techniques for embedded memories thus are important for SoC. Embedded memories have become very vulnerable to even minor process variations, resulting in low manufacturing yield & reliability. The BISR includes the BIST, BIRA module. The BIRA circuit performs the redundancy allocation using the proposed RA algorithm. The purpose of RA is to allocate appropriate redundant (spare) memory elements to replace the defective cells, such that the utilization of the spare elements can be optimized. In a memory with BISR, the RA collects the fault information from the BIST. RA performs the analysis after the fault bit-map of a defective memory is constructed. In this paper, it is proposed to model a RA technique for 2D Random Access Memory of 512 bit with spare rows and columns. This Analyzer decides which spare element to be allocated for a fault adaptively by considering the fault count on each row/column. The above model will be simulated using Aldec Active HDL version 6.3 and synthesised using Xilinx ISE tool. Top Keywords Built in Self-test, Built in Self Repair(BISR), Redundancy Analyzer, Redundancy Analysis, Spare elements, System on chip, 2Dimensional, fault bit map, defective memory, defective cell. Top |