International Journal of Engineering and Management Research (IJEMR)
Year : 2017, Volume : 7, Issue : 5
First page : ( 178) Last page : ( 190)
Print ISSN : 2394-6962. Online ISSN : 2250-0758.

Technique for Designing High Speed Noise Immune CMOS Domino High Fan-in Circuits

Lakshmi A. Chaitanya¹, Nausheen Saba¹, Renuka M.¹

¹Assistant Professor, ECE Department, Vidya Jyothi Institute of Technology, JNTU, Hyderabad, India

Online published on 8 December, 2017.

Abstract

Dynamic logic circuits provide more compact designs with faster switching speeds and low power consumption compared with the other CMOS design styles. Domino logic overcomes the difficulties in dynamic circuits such as charge sharing and cascading. In this paper we are proposing a wide fan-in circuit with increased switching speed and noise immunity. Speed is achieved by quickly removing the charge on the dynamic node during evaluation phase, compared to the other circuits. The design also offers less Power Delay Product (PDP). The design is exercised for 20% variation in supply voltage. The design shows a 1.83% improvement in Average Noise Threshold Energy (ANTE). Using the proposed technique an Octal-to-binary encoder is designed and simulated.

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Keywords

CMOS design, Power Delay Product, Average Noise Threshold Energy.

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