A novel high speed adder architecture implementation using HDL Abhilash J.E.N.*, Ajay D**, Surendra T***, Tanuja T****, Ashok K**** *B. Tech Program, Electronics and Communication Engneering **Andhra Pradesh, India ***Associate Professor, Dept Electronics And Communication Engineering ****Swarnandhra College Of Engneering And Technology, Narsapur, West Godavari Dst, Andhra Pradesh Online published on 24 October, 2019. Abstract This paper presents an efficient high speed parallel single-rail self-timed adder. It is based on a recursive formulation for performing multi-bit binary addition. The operation is parallel for those bits that do not need any carry chain propagation. Thus, the design attains logarithmic performance over random operand conditions without any special speedup circuitry or look-ahead schema. A practical implementation is provided along with a completion detection unit. The results are implemented and verified using standard Xilinx14.5 using ISE Simulator and results are compared with RCA. By observing the implementation the speed has increased 63.3% than existing work. Top Keywords Parallel self timed adder (PASTA), Xilinx, Mentor graphics, Carry chain propagation. Top |