To Reduce SRAM Sub-Threshold Leakage Using Stack and Zig-Zag techniques Venigalla Sai Praveen1, Vemana G. Santhi Swaroop2, Babu M. Nagesh3 1M. TECH Student, Department of ECE, K.L. University, Guntur, Dt. AP, India 2M.TECH Student, Department of ECE, K.L. University, Guntur, Dt. AP, India 3Dept. of ECE, K.L. University, Vijayawada, India Online published on 4 November, 2017. Abstract The growing market of portable electronics devices demands lesser power dissipation for longer battery life and compact system. Considerable attention has been given to the design of low-power and high-performance SRAMs since they are critical components in both high-performance processors and hand-held portable devices. The reduction of the threshold voltage due to voltage scaling leads to increase in sub threshold leakage current and hence static power dissipation. The leakage current consists of reverse-bias diode currents and sub threshold currents. Scaling down of threshold voltage results in exponential increase of the sub threshold leakage current. This paper presents a method based on controlling the leakage currents by using effective stacking of transistors using stack technique and another method based on zig-zag approach. The proposed stack technique forces a stack effect by breaking down an existing transistor into two half size transistors. When the two transistors are turned off together, induces reverse bias between the two transistors results in sub-threshold leakage current reduction. The Zig-Zag technique reduces wake-up overhead caused by sleep transistors by placement of alternating sleep transistors, assuming a particular pre-selected input vector. The simulation results have been carried out using microwind tool on 90 nm technology. Top Index Terms SRAM, Stack Technique, Zig-Zag Technique, Low Power. Top |