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Superiority of Current mode over Voltage mode Interconnects Agrawal Yash*, Dhiman Rohit**, Chandel Rajeevan*** Department of Electronics & Communication Engineering, National Institute of Technology, Hamirpur-177 005, Himachal Pradesh, India *mr.yashagrawal@gmail.com
**rohitdhiman.nitham@gmail.com
***rajevanchandel@gmail.com
Online published on 4 November, 2017. Abstract In deep submicron VLSI circuits, interconnect delays dominate MOSFET gate delays. Conventional buffer insertion method reduces delays at the cost of valuable chip area. Consequently, alternative methods are essential. Current mode interconnects have lesser delay than voltage mode circuits and also consume lesser chip area. In the present work, superiority of current mode over voltage mode interconnects is analyzed. The simulative analysis is carried out using Tanner EDA tools. Top | |
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