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Design and Implementation of Low Power Phase Frequency Detector (PFD) for PLL Nidagundi Jayashree*, Desai Harish**, Shruti A.***, Manik Gopal**** Department of Electronics and Communication Engineering, Shri Dharmasthala Manjunatheshwara College of Engineering and Technology, Dharwad, Karnataka, India *Email id: jayaprajwal@rediffmail.com
**harimd01@gmail.com
***shrusweetu@gmail.com
****gopalmanik@gmail.com
Online published on 4 November, 2017. Abstract This paper presents a novel Phase frequency detector for Charge Pump Phase locked loop (PLL) applications to enable fast frequency acquisition in the phaselocked loop (PLL). To cope with the missing edge problem, the proposed PFD predicts the reset signal and blocks the corresponding input signal during the reset time. The blocked edge is regenerated after the reset signal is deactivated [1]. The PFD will be implemented using 0.18 μm technology. The designed PFD can be used in PLL with Frequency up to 1.5GHz. The results reported in this paper based on simulation done using Cadence Assura layout tool. Top Keywords Low power, Phase frequency detector (PFD), phase locked loop (PLL), Cadence, Assura. Top | |
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