Design of Low Power FFT Processor for OFDM Wireless Communication Systems Kumar S. Nirmal*, Santhosh B.K. Department of Electronics & Communication Engineering, Jaya Engineering College, Prakash Nagar, Chennai-602024 *imnirmal.58@gmail.com
Online published on 4 November, 2017. Abstract The demand for high-speed mobile wireless communications is rapidly growing. OFDM technology promises to be a key technique for achieving the high data capacity and spectral efficiency requirements for wireless communication systems of the near future. Fast Fourier transform (FFT) processing is one of the key procedures in popular orthogonal frequency division multiplexing (OFDM) communication systems. Structured pipeline architectures, low power consumption, high speed and reduced chip area are the main concerns in this VLSI implementation. In this paper, the efficient implementation of FFT processor for OFDM applications is presented. This processor can be used in various OFDM-based communication systems, such as Worldwide Interoperability for Microwave access (Wi-Max), digital audio broadcasting (DAB), digital video broadcasting terrestrial (DVB-T). The three processing elements (PE's), delay-line (DL) buffers are used for computing FFT. Thus we consume low power, low hardware cost high efficiency and reduced chip size. Top Keywords FFT, PE, Twiddle Factor, OFDM, Modified Booth Multiplier, SDF, Radix-2&4. Top |