Power and energy efficient Flip-Flops using floating gate and quasi floating gate techniques at 180nm Kumari Sweta1, Sharma Shobha1,*, Dev Amita2 1Department of Electronics and Communication, Indira Gandhi Delhi Technical University For Woman, Kashmere Gate, New Delhi, India 2Principal, BPIBS, Shakarpur, Delhi, India *Corresponding author
Online published on 24 May, 2018. Abstract The objective of this research is to know the effectiveness of floating gate technique and quasi floating gate technique on various types of flip flops on lowering power dissipation, propagation delay and/or power delay product. The analysis is done on the experimental results obtained using Cadence virtuoso simulator at 180nm CMOS technology. It is found that the propagation delay is reduced by 76% and PDP is reduced by 77% in Dual edge Triggered Flip Flop with floating gate technique. The PDP is reduced by 45% with quasi floating gate technique in this flip flop. The reduction in PDP is 47% with floating gate technique in TSPC flip flop. With quasi floating gate technique, this reduction in PDP is 68.7% in TSPC flip flop. In semi dynamic flip flop the reduction in PDP is only 0.8% with floating gate technique and almost negative impact of quasi floating gate technique. For the first time this study finds an impact of FG and QFG techniques in various types flip flops in reducing power dissipation and PDPat 180nm technology node. This study could further be extended in subthreshold region for further reduction in power dissipation and PDP. Also this study shows that FG and QFG is not always effective in reducing power and effectiveness varies from circuit to circuit. This reason could be analyzed further as the future scope of the paper. Top Keywords Dual edge triggered Flip Flop, Semi dynamic Flip Flop, True single phase clocking, Floating gate technique. Top |