Design and FPGA Implementation of Systolic Array Architecture for Full Search Block Matching Algorithm Prakash S.1, Kumar R. Selva2, Murthy Vasudeva3 1M. Sc. [Engg.] Student, VLSI System Design Centre, M.S. Ramaiah School of Advanced Studies, Bangalore, 560 054 2 Senior Lecturer, VLSI System Design Centre, M.S. Ramaiah School of Advanced Studies, Bangalore, 560 054 3 Senior Lecturer, VLSI System Design Centre, M.S. Ramaiah School of Advanced Studies, Bangalore, 560 054 Online published on 18 February, 2020. Abstract In digital video coding applications, adjacent frames look similar and changes are due to the movement of the object or the camera. So their spatial and temporal redundancy must be exploited to obtain reduced data to store and transmit. The motion between two consecutive images can be estimated using Full Search Block Matching Algorithm (FSBMA). This algorithm determines motion by pixel-by-pixel basis. Systolic array architecture can be used to implement the Full Search Block Matching Algorithm due to their advantageous properties like regularity, modularity and local communication. The FSBMA has been designed using two dimensional systolic array architecture. The blocks of this architecture are processing element, shift register arrays, address generators for search area value, reference block value, enable signal generator, candidate region monitor and best match selection unit. All these blocks and the top module have been designed. In this work the two dimensional systolic array architecture with serial input is used to perform Full Search Block Matching Algorithm. The FSBMA using Systolic Array has been modeled in Verilog Hardware Description Language and simulated against its functional specifications. This is then synthesized using Xilinx synthesis tool with constraints and has been implemented on FPGA. The implemented design has been verified. The system has a single clock and reset. The designed system has an image resolution of 176x144 and works at a frequency of 45.792MHz. It takes serial inputs and performs parallel processing to reduce IO pin counts. The design has been implemented on Spartan3E FPGA and the following resources have been utilized-2095 out of 4656 slices (44%), 2816 out of 9312 slice flip-flops (30%) and 63 Input Output blocks (IOBs). The minimum period of one clock pulse is 21.838ns. Top Keywords Motion Estimation, Full Search Block Matching Algorithm, Systolic Array. Top |